Many integrated circuits use clock distribution networks to distribute clock signals to a multitude of circuit components on the die. Many techniques for distributing high frequency clock signals in an integrated circuit generate clock skew.
FIG. 1A illustrates an example of the clock skew that a typical prior art clock distribution network generates in a clock signal transmitted through the network. As the clock signal propagates through the clock distribution network, the phase of the clock signal can become significantly offset relative to its starting phase. In the example of FIG. 1A, the phase of the clock signal becomes offset by 200° from its starting phase. In the graphs shown in FIGS. 1A and 1B, the horizontal axes represent the length of the clock network.
A delay-locked loop can be coupled to a clock distribution network to reduce the clock skew and to reduce voltage amplitude variations in a clock signal. However, a conventional delay-locked loop uses several delay circuits to generate an output clock signal. The delay circuits consume power and add power supply induced jitter into the output clock signal.
The distribution of a high frequency clock signal in an integrated circuit can generate significant variations in the voltage amplitude of the clock signal. FIG. 1B illustrates an example of the variations in the voltage amplitude of a clock signal transmitted through a typical prior art clock distribution network. In this example, the voltage amplitude of the clock signal attenuates along the length of the clock distribution network. In the examples of FIG. 1A-1B, the clock distribution networks are terminated.
Many clock distribution network designs, such as H-tree and meshed clock networks, consume a large amount of power and die area on the integrated circuit. Also, many clock distribution networks, such as H-tree clock networks, can be laid out on an integrated circuit in only one configuration or in only a limited number of configurations.